The invention relates to a memory having a line decoder which comprises for each line a Darlington-type line switching stage, comprising a first transistor whose base forms the input of the stage and serves to receive a logic control signal whose voltage varies between a level which is referred to as the selection level and a level which is referred to as the non-selection level, its emitter being connected to the base of a second transistor whose emitter constitutes the output of the stage and is connected to an upper line conductor in which a first current flows when said logic control signal has the selection level, while a second current which is smaller than the first current flows therein when said logic control signal has the non-selection level. In this stage there are arranged, between the base of the second transistor and an auxiliary current source for a current intensity between that of the second current and the first current, a first and a second diode which are connected in series and in the forward direction and which form a first branch. In this stage there is also arranged, between the emitter of the second transistor and said auxiliary current source, a third diode which is connected in the forward direction and which constitutes a second branch so that, when the control signal of a said line is switched between its selection level and its non-selection level, the charges stored in the base of the second transistor are drained by the current of the auxiliary current source, the major part of which enters the first branch.
A memory of this kind is described in French Patent Application No. 85 05 702, filed on Apr. 16, 1986, and entitled "Etage de commutation de type Darlington notamment pour un decodeur de lignes d'une memoire". The corresponding U.S. Pat. No. 4,706,222. The memories essentially covered by said Application are essentially fast memories comprising a reduced number of lines.
However, it may also be advantageous to realize a Darlington-type switching stage as described for other types of memory, having a longer switching time, in order to improve the deselection of the lines and to achieve also the supplementary advantage of a greater gap between the level corresponding to the selected mode and the level corresponding to the non-selected mode.
It has been found that in given cases dysfunctioning could occur at the level of the deselected lines of an active charge memory (ECL) or resistive charge memory.
Such dysfunctioning consists in the inverse saturation of a transistor of a half-cell of each cell of the deselected line or lines. This phenomenon is particularly disturbing, because if the desaturation of the pnp transistor of an ECL half-cell is particularly slow in the normal saturation mode, that is to say direct, desaturation will even be slower in the inverse saturation mode. It is, moreover, a paradox in that the improvement of the deselection speed of the lines of a memory is always considered to be advantageous. In the case of a resistive charged memory, the inversion of the pnp transistor of a half-cell also constitutes a drawback.
The cause of such dysfunctioning has been determined to be due to the fact that when the cell has an intrinsic switching time constant which is notably longer than the deselection time constant of the lines, the level of its upper line conductor may be temporarily lower than the internal high level of the memory cell and, in given cases, even lower than the level of its lower line conductor; in the first case this causes the pnp transistor of an ECL half-cell to enter the inverse saturation mode, and in the second case a complete half-cell to enter the direct inverse mode.